1. Field of the Invention
The present invention relates to a current mode pulse width modulation (PWM) boost circuit and a feedback sensing method thereof. More particularly, the present invention relates to a current mode PWM boost circuit having functions of directly sensing an inductor current and a slope compensation ramp signal and a feedback sensing method thereof.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98.
FIG. 1 shows a conventional current mode pulse width modulation (PWM) boost circuit 10, which includes a boost circuit 11, a voltage dividing circuit 19, an error amplifier 12, a comparator 13, an inductor current generator 14, a slope compensation ramp generator 15, an oscillator 16, a pulse width generator 17, and a buffer 18. A voltage VIN is increased by the boost circuit 11 to generate a higher DC output voltage VOUT. The boost circuit 11 includes an input capacitor C1, a boost inductor L, a MOS transistor T, a rectifying diode D, and an output capacitor C2. The input capacitor C1 is used to filter out ripple voltage from the voltage VIN. When the MOS transistor T is turned on, the rectifying diode D has a reverse bias. At this time, a current flows through the boost inductor L forward, such that the voltage on the boost inductor L increases. However, the current does not flow through the boost inductor L in an instant, but increases linearly and forms an electromagnetic field. At this time, when the MOS transistor T is turned on, the output current is provided by the output capacitor C2 only. When the MOS transistor T is turned off, the boost inductor L cannot store energy, so the electromagnetic field stored in the boost inductor L is released. Thus, the polarity of the voltage on the boost inductor L is inverted, such that the boost inductor L releases the stored energy to the output capacitor C2, and a voltage at a terminal (i.e., the node N3) of the rectifying diode D that is connected to the boost inductor L is higher than the voltage VIN. This energy provides a load current, and meanwhile charges the output capacitor C2 again. The voltage dividing circuit 19 includes two resistors R1 and R2, which are connected in series. A divided voltage VF1 is acquired at a node N2 that connects the resistors R1 and R2, and is sent to the error amplifier 12 where the divided voltage VF1 is compared with a reference voltage VREF to generate an error signal E0. After that, the error signal E0 is compared with a feedback signal VSUM by the comparator 13. The output of the comparator 13 (i.e., VF2) and an oscillation signal S1 coming from the oscillator 16 are input into the pulse width generator 17 together. A driving signal SDR generated by the pulse width generator 17 passes through the buffer 18 to generate a gate control signal SG, so as to adjust the conductive time of the MOS transistor T (i.e., to adjust the pulse duration of the driving signal SDR), and further to control the DC output voltage VOUT.
The inductor current generator 14 receives a voltage signal VSEN from the node N3, and the voltage signal VSEN is processed by a voltage-to-current transfer structure (e.g., a resistor or a transconductance amplifier) therein to generate an inductor current ISEN flowing through the boost inductor L. FIGS. 2(a)-2(c) illustrate different access points N31, N32, and N33 of the voltage signal VSEN in the conventional art. The method to capture the voltage signal VSEN of FIG. 2(a) is more accurate than the methods of the other two figures, but consumes more power. The methods to capture the voltage VSEN of FIGS. 2(b) and 2(c) are lossless and better than the method of FIG. 2(a), but respectively have problems of lower accuracy and matching. Moreover, after the voltage signal VSEN is processed by the inductor current generator 14, the inductor current ISEN may be easily distorted. Furthermore, the slope compensation ramp generator 15 is directed to solving problems such as open-loop instability, sub-harmonic oscillation, and noise sensitivity in current mode converters when operating in continuous conduction mode with a duty cycle of the driving signal SDR larger than 50%. The slope compensation ramp generator 15 receives an oscillation signal S2 from the oscillator 16, and the oscillation signal S2 is processed by a voltage-to-current transfer structure (e.g., a transconductance amplifier) therein to generate a slope compensation ramp signal ISLO. Similarly, after being used by the slope compensation ramp generator 15, the slope compensation ramp signal ISLO may be easily distorted. Finally, the inductor current ISEN and the slope compensation ramp signal ISLO flow through a resistor Rf, and generate the feedback signal VSUM at a node N1.